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  2. 村松 大吾

村松 大吾

ムラマツ ダイゴ  (Daigo Muramatsu)

基本情報

所属
成蹊大学 理工学部 理工学科 教授
学位
博士（工学）(2006年2月 早稲田大学)
J-GLOBAL ID
200901008108953941
researchmap会員ID
5000098390

研究キーワード

 2

研究分野

 3

経歴

 6
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学歴

 6
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受賞

 7
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論文

 89
  • Susumu Kikkawa, Fumio Okura, Daigo Muramatsu, Yasushi Yagi, Hideo Saito
    IEEE Access 11 19312-19323 2023年  査読有り
  • Ryosuke Hasegawa, Akira Uchiyama, Fumio Okura, Daigo Muramatsu, Issei Ogasawara, Hiromi Takahata, Ken Nakata, Teruo Higashino
    IEEE Access 10 15457-15468 2022年2月  査読有り
  • Daigo Muramatsu, Kousuke Moriwaki, Yoshiki Maruya, Noriko Takemura, Yasushi Yagi
    BIOSIG 2022 - Proceedings of the 21st International Conference of the Biometrics Special Interest Group 213-220 2022年  査読有り
    CNN is a major model used for image-based recognition tasks, including gait recognition, and many CNN-based network structures and/or learning frameworks have been proposed. Among them, we focus on approaches that use multiple labels for learning, typified by multi-task learning. These approaches are sometimes used to improve the accuracy of the main task by incorporating extra labels associated with sub-tasks. The incorporated labels for learning are usually selected from real tasks heuristically; for example, gender and/or age labels are incorporated together with subject identity labels. We take a different approach and consider a virtual task as a sub-task, and incorporate pseudo output labels together with labels associated with the main task and/or real task. In this paper, we focus on a gait-based person recognition task as the main task, and we discuss the effectiveness of virtual tasks with different pseudo labels for construction of a CNN-based gait feature extractor.
  • Ryosuke Hasegawa, Akira Uchiyama, Fumio Okura, Daigo Muramatsu, Issei Ogasawara, Hiromi Takahata, Ken Nakata, Teruo Higashino
    Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering 481-486 2022年  
  • Yasushi Makihara, Yuta Hayashi, Allam Shehata, Daigo Muramatsu, Yasushi Yagi
    2021 IEEE International Joint Conference on Biometrics (IJCB) 2021年8月4日  査読有り
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MISC

 109
  • 近藤充, 村松大吾, 佐々木昌浩, 松本隆
    電子情報通信学会総合大会 D-12-25 186 2003年  
  • A Sakamoto, M Kondo, H Morita, D Muramatsu, M Sasaki, T Matsumoto
    ICONIP'02: PROCEEDINGS OF THE 9TH INTERNATIONAL CONFERENCE ON NEURAL INFORMATION PROCESSING 2078-2082 2002年  
    Authentication of individuals is rapidly becoming an important issue. The authors have previously proposed a pen-input on-line signature verification algorithm incorporating pen-position, pen-pressure and pen-inclination trajectories. This paper proposes an algorithm with three new features: (i) Incorporation of pen-velocity trajectories, (ii) A new distance measure between two signatures, and (iii) A new efficient algorithm for computing the distance measure. Preliminary experimental result looks encouraging.
  • 佐々木昌浩, 村松大吾, 松本 隆, Hadidi Khayrollah
    電子情報通信学会エレクトロニクスソサエティ大会講演論文集 2 83 2001年  
  • Khayrollah Hadidi, 佐々木 昌浩, 渡辺 忠敏, 村松 大吾, 松本 隆
    電子情報通信学会ソサイエティ大会講演論文集 2000(2) 105-105 2000年9月7日  
  • K Hadidi, M Sasaki, T Watanabe, D Muramatsu, T Matsumoto
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E83A(2) 261-266 2000年2月  
    Based on a cascode-driver source-follower buffer and a passive sampling architecture, we have implemented a differential sample-and-hold circuit in a 0.8 mu m digital CMOS process. The buffer which eliminates channel length modulation of the driver device behaves very linearly, in low frequencies or sampled-data applications. This is the main reason that this first open-loop CMOS sample-and-hold can achieves very high linearity while functions at very high sampling rate. The circuit achieved -61 dB THD for a 1.42 Vp-p 10 MHz input signal at a 103 MHz sampling rate and -55.9 dB THD for a 1.22 Vp-p 20 MHz at a 101 MHz sampling rate.
  • Khayrolla Hadidi, 佐々木昌浩, 渡辺忠敏, 村松大吾, 薊純一郎, 松本 隆
    第１２回回路とシステムワークショップ論文集 43-47 1999年  
  • Kh. Hadidi, D. Muramatsu, T. Oue, T. Matsumoto
    25th European Solid-State Circuits Conference (ESSCIRC '99) 158-161 1999年  
  • K Hadidi, M Sasaki, T Watanabe, D Muramatsu, T Matsumoto
    IEEE 1998 CUSTOM INTEGRATED CIRCUITS CONFERENCE - PROCEEDINGS 381-383 1998年  
    Based on a real open loop architecture and a cascode-driver CMOS source-follower, we implemented a S/H circuit in a 0.8 mu m digital CMOS process. The circuit achieved -61dB THD at a sampling rate of 103MHz, while a 1.42V(p-p) 10MHz input signal was applied. This includes all parastic loading and transient effect.
  • Kh. Hadidi, J. Sobhi, A. Hasankhaan, D. Muramatsu, T. Matsumoto
    International Conference on Electronics, Circuits and Systems(ICECS) 3 369-371 1998年  

所属学協会

 6
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共同研究・競争的資金等の研究課題

 9
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