上浦 尚武

Truncated sum (TSUM for short) can be useful for MV-PLAs realization. This paper introduces multiple-valued product-of-sums expressions where sum refers to TSUM and product does MIN. We investigate the multiple-valued product-of-sums expressions and show the minimization method and the simulation results. We describe the minimization method based on binary Quine-McCluskey algorithm. It is proved that in the minimal product-of-sums expressions, the implicate number of the expressions with TSUM is equivalent to the number of those with MAX. Next, we propose multiple-valued product-of-sums expressions with variables. The expressions involve the TSUM of variables and nonzero constants as the coefficients of the implicates. The minimization method is also proposed. Finally, we show the simulation results for some multiple-valued arithmetic functions. In them, an efficiency of the product-of-sums expressions with variables is shown and some comparisons are made.

This paper presents a novel model to detect the deepest point of a ditch as cerebral sulcus. Our model demonstrates magnetic behavior and consists of four ideal magnetic pales: an N-pole and three S-pales. Due to their Coulomb forces as the inverse square of the distance, one of S-poles automatically reaches the deepest point of the ditch, This model can also detect the point in case of ditch with implicit branches. Our experimental results an sliced human brain MR images show that our method can detect the paints at 90% correct detection ratio.

This paper presents a robust automatic threshold finding method for the human brain MR image segmentation. The method is based on fuzzy information granulation shown by Zadeh. The human brain MR image consists of several parts; the gray matter, white matter, cerebrospinal fluid and so on. By treating their parts as the fuzzy granules in the gray level histogram of the image and developing fuzzy matching technique, we can find required thresholds and can segment the brain region from the MR image. An experiment is done on 50 gray level histograms of the human brain MR volumes. To evaluate our method, we extract the brain region using the obtained thresholds. A comparison of the obtained region with canonical atlas images shows that our method find the thresholds of the gray matter and white matter correctly.

脳外科分野において手術計画を立てるとき,腫瘍等対象部位から脳表面のしわの奥までの距離が重要な情報となる.MRIは脳内軟部組織を高いコントラストで撮影できるので,それにより脳形状等の複雑な情報が正確に得られる.本文では,MR断層画像を基に構成した3次元画像を平面で切断し,切断面の断層像から脳内部位-脳表面しわ間の距離を測定する方法を提案する.

フェイルセイフ論理系の一つとして,1/2をとる入力が一つでもあれば出力値が1/2となるC型フェイルセイフが提案されている.本文ではこの概念を基本とし,故障が生じれば,正常値または安全状態1/2を出力する多値セルラアレーを提案する.

In this paper, we discuss problems in design and fault masking of multiple-valued cellular arrays where basic cells having simple switch functions are arranged iteratively. The stuck-at faults of switch cells are assumed to be fault models. First, we introduce a universal single-level array and derive the ratio of the number of single faults whose influence can be masked to the total number of single faults. Next, we propose a universal two-level array that outputs correct values even if single faults occur in it and derive the ratio of the number of double faults whose influence can be masked compared to the total number of double faults. By evaluating the universal singlelevel array and the universal two-level array from the viewpoints of design and fault masking, we show that the latter is superior to the former. Finally, we compare our universal twolevel array with formerly presented arrays in order to demonstrate the advantages of our universal two-level array.

The purpose of this paper establishes a method to decompose the brain region into the inherent portions. In it fuzzy inference is used to evaluate what portion each voxel belongs to. We develop a decomposition method based on standard region growing algorithm, which requires the inference results. The comparison of the volumes of our extracted portions with manually measured volumes by a medical doctor shows that on the average, the error rate is 2% for some MRI data.

In the field of medical science, the extraction of the brain regions from MR images is valuable to diagnose: an Alzheimer's disease. We propose here a novel approach to extract the brain region using the fuzzy matching technique. We describe a modeling of the intensity histogram by fuzzy logic and evaluate fuzzy matching techniques for the extraction of the brain region. We develop the extraction algorithm based on a standard region growing technique. An experimental result on 36 MRI data shows that the error rate is 2.4%, on the average, against manually extracted volumes by a medical doctor.

In this paper, we discuss the design of a fai-safe cellular array composed of switch cells. First, we show the design method using a binary decision diagram. Next, we assume stuck-at faults of switch cells to be fault models and discuss the fail-safe property for our array. For all the single faults and part of the multiple faults, our array keeps the fail-safe property. Next, for our arrays realizing randomly generated functions, we derive the ratio of the number of double faults that never break the fail-safe property to the total number of double faults. Finally, in order to demonstrate the advantages of our array, we compare our array with other arrays.

In this paper, we discuss easily testable cellular arrays that are constructed from Multiple-valued Decision Diagrams (MDD's). The cellular arrays consist of cells having simple switch functions. Since control inputs that specify switches of cells are determined easily by tracing paths activated in MDD's, our method for constructing cellular arrays is simple. We propose faults tests for multiple stuck-at faults of switch cells. We can locate any row having at least one faulty cell. We apply our array to the realizations of numerous binary and multiple-valued logic functions and compare our array with other cellular arrays.

In this paper, we propose a method to design ternary cellular arrays by using Ternary Decision Diagrams (TDD's). Our cellular array has a rectangular structure composed of ternary switch cells. The ternary functions represented by TDD's are realized by mapping the TDD's to the arrays directly. That is, both the nodes and the edges in the TDD are realized by some sets of the cells. Since TDD's can represent easily multiple-output functions without large memory requirements, our arrays are suitable for the realization of multiple-output functions. To evaluate our method, we apply our method to some benchmark circuits, and compare our arrays with the ternary PLA's. The experimental results show that our arrays have the advantage for their sizes, especially in the realization of symmetric functions. The results also clarify that the size of our arrays depends on the size of TDD's.

An input permutation technique with respect to multiple-valued logic synthesis is introduced. First, it is applied to multiple-valued sum-of-products expressions where sum refers to TSUM. Some upper bounds are clarified on the number of implicants in minimal sum-of-products expressions for one-variable and two-variable functions with permuted logic values. An experiment was done on randomly generated functions. The result shows that we can have a saving of approximately 15% on the average by permuting input values. Next, we compare the input permutation with output permutation. As a result, input permutation and output permutation yield a similar saving rate of implicants and output permutation has an advantage of hardware cost and minimization times. Moreover, we show that the use of input permutation for multiple-valued sum-of-products expressions with window literals yields similar results when one uses sum-of-products expressions with set literals.

An approach to logic minimization using a new sum operation called multiple-valued EXOR is proposed. This paper introduces the multiple-valued sum-of-products expression using the EXOR. As the scheme of the minimization, we utilize an idea based on neural computing. First, we demonstrate the method to minimize the binary EXOR-of-MIN's expressions and show that the method is effective. Next, we apply the method to the three-valued EXOR-of-MIN's expression. Experimental results for all three-valued two-variable functions show that our proposed multiple-valued EXOR-of-MIN's expressions require fewer product terms than both the MAX-of-MIN's and TSUM-of-MIN's expressions.

This paper proposes a method to design ternary cellular arrays with high testability. In it, stuck-at faults of switch cells are assumed. Testing of the array composed of switch cells can be executed easily because of the regular structure of the array. Moreover, if a faulty cell is identified, we can isolate the faulty cell from the remaining cells. The ternary functions represented by Ternary Decision Diagrams (TDD's) are realized by mapping the TDD's to the cellular arrays directly. Proposed arrays are more advantageous than ternary PLA's for their sizes in realizations of symmetric functions and are also useful for the realizations of multiple-output functions.

An efficient fault diagnostic method should be developed to reduce the turnaround time and the cost for developing binary LSI's. For the multiple‐valued logic system that has been expected in the post‐binary electronics, research on the fault diagnosis for the logic circuit will be essential. This paper discusses the design and the fault diagnosis in multiple‐valued cellular arrays. First, the single‐level array, two‐level array, three‐level array, and n‐level array realizing k‐valued n‐variable logic functions are introduced. It is clarified that the two‐level array is the most suitable structure solving both problems of the number of cells and the fault location. Next, further investigation is made for the fault diagnosis. The stuck‐at faults, the open fault, and the AND bridging fault are treated under the assumption that the single fault occurs in the array. In the authors' fault diagnostic method, the test inputs can easily be generated from the control inputs that specify the switches of cells. Moreover, the comparison with other testing methods for cellular arrays shows that our method reduces the order of steps for generating all test inputs. Copyright © 1994 Wiley Periodicals, Inc., A Wiley Company

This paper discusses the problems of the design and the fault tolerance in multiple-valued cellular arrays by considering the single-level array, the two-level array and the three-level array. These arrays are constructed by some cells that have the unique switch operation. It assumes the stuck-at-0 fault and the stuck-at-(k-1) fault of the switch cells on k-valued cellular arrays. The fault-tolerant arrays for the single fault are constructed by building a duplicate row and a duplicate column iteratively in the arrays. By evaluating three types for the design, the fault tolerance and the testability for multiple faults, it clarifies that the two-level array is the most suitable structure. Finally, the comparison with formerly presented arrays shows advantages for our fault-tolerant two-level array.

2値LSIの開発においては,設計期間の短縮やコストの低減のために,効率の良い試作段階での故障診断法の開発が必要になっている.ポストバイナリエレクトロニクスの有力候補である多値論理システムにおいても,論理回路の故障診断は重要な研究分野になると考えられる.本論文では多値セルラアレーの設計とその故障診断について考察する.まず.k値n変数関数を実現する回路構造として1段アレー回路,2段アレー回路網,3段アレー回路網,n段アレー回路網を考える.次に,これらの中で2段アレー回路網がセル数と故障セルの位置指摘の両方において最も有効な回路構造であることを明らかにする.そしてこの回路構造の故障診断方法について考察する.本論文では単一故障の仮定のもとでセルのスイッチの縮退故障,オープン故障,ANDブリッジ故障を取り扱う.このとき,この回路構造の検査入力は,セルのスイッチ動作を決定する制御入力から容易に生成できること,また他の文献のセルラアレーに対する検査法との比較により,本方法はすべての検査入力の生成に必要な計算ステップ数に関して利点をもつことが示された.

A method is proposed for realizing any k-valued n-variable function with a cellular array, which consists of linear arrays (called input arrays) and a rectangular array (called control array). In this method, a k-valued n-variable function is divided into k(n-1) one-variable functions and remaining (n-1)-variable function. The parts of one-variable functions are realized by the input arrays, remaining the (n-1)-variable function is realized by the control array. The array realizing the function is composed by connecting the input arrays with the control array. Then, this array requires (k+n-2)k(n-1) cells and the number is smaller than the other rectangular arrays. Next, a ternary cell circuit and a literal circuit are actually constructed with CMOS transistors and NMOS pass transistors. The experiment shows that these circuits perform the expected operations.

本論文では, ファジィコンピュータの基礎研究としてプログラマブル・ロジック・アレイ(PLA)に注目し, ファジィ論理関数を実現するファジィ PLA の提案を行う.ファジィ論理関数は, ファジィ AND, OR, NOT, 変数によって構成されるファジィ論理式で表現可能な関数であり, 現在, その簡単化法や代数的性質の解明等種々の研究がなされている.本論文では P 形論理関数, C形論理関数に代表される, 工学上重要な意味を持つ特別なクラスのファジィ論理関数を考え, これらをファジィ PLA で実現するための回路設計法について述べる.まず, 2値の PLA として標準的な AND-OR 型の PLA をファジィ論理に適用した AND-OR ファジィ PLA を提案する.そして任意の多出力 n 変数ファジィ論理関数が3^n+n-1の列数で実現できることを示す.次に, PLA の列数は回路コストへ直接影響するため, この最大列数を最小化することを考える.そこで, AND-OR 型のファジィ PLA と OR-AND 型のファジィ PLA を相互接続し, 更に出力デコーダを付加した AND-OR/OR-AND ファジィ PLA の提案を行う.そして, この PLA は2^<n+1>の列数で任意の多出力ファジィ論理関数が実現できることを示す.このように AND-OR/OR-AND ファジィ PLA は AND-OR 型のファジィ PLA に対して列数の上限が小さくなること, また, 変数の数が増すほど有効となることを明らかにする.

This paper proposes a diagnosable and repairable k-valued cellular array. We assume a single fault, i.e., either stuck-at-0 fault or stuck-at-(k-1) fault of switches occurs in the array. By building in a duplicate column iteratively, we can construct a fault-tolerant array for the stuck-at-(k-1) fault. Therefore, since we don't have to diagnose the stuck-at-(k-1) fault, the diagnosing method is simple and easy. Furthermore, our array can be repaired easily by a systematic procedure. The comparison with other rectangular arrays clarifies that our array has advantages for the number of cells and the steps of generating all test inputs.

An easily testable k-valued cellular array consisting of input arrays and a control array that requires fewer cells than other methods is proposed. Stuck-at, open, and AND bridging faults are treated under the assumption that a single fault occurs in the array. Test input vectors can be easily generated from control inputs that specify the switches of cells. It is shown that a faulty cell can be effectively diagnosed by using several observable terminals and (k + 1)-valued logic values.