Shusuke Okamoto

Applying cache to multiprocessor is one of the solution to improve latency with remote memory access. But the line size of the cache is the unit of storage reference and the cache cannot control by user program, it cannot get maximum performance. To solve this problem, we have already proposed Program Controlled Cache Memory on Parallel Computer. This memory system can migrate data between high speed memory as fast as cache memory and NUMA-type shared memory by the program for data migration. This memory system is composed by word-addressable high speed memory (Cache Level Memory) and hardware mechanism which executes instructions to migrate variable sized data. In this paper, we describe a programming method for cache coherence protocol less parallel computer.

To reduce the cache miss penalty, which becomes heavy bottleneck for processor, we have proposed new hierarchical memory system, we can UPCHMS. UPCHMS enables memory to supply the data to processor faster. than cache memory system does. The reason why UPCHMS can do this shows follow. In UPCHMS, data transfer program, controls the data on the HM, which corresponds to cache memory and has no main memory address but has its own linear address. It is possible for program-control to use the data on HM more efficiently. In this paper, we describe the UPCHMS with pipelineing.

We've proposed a new hierarchical memory system, which consists of three level memories. This system has two kinds of programs. One is target program which executes arithmetic and logical part. Another is data transfer programs which control data mapping and transfer between different levels of hierarchical memories by one word. Furthermore, data transfers are done in parallel with the target program. Therefore, it is possible for this system to prepare necessary data into upper level memory before the target program refers to them. This paper describes mainly the analyzing for this system's features.

A latency with remote memory access is one of the problem on the design of Parallel Computer. To solve this problem, Data prefecthing to data cache has already proposed. But Prefetching cannot handle inefficient cache usage and invalid traffic on cache coherence protocol. To improve these problems, We have already proposed Program Controlled Cache Memory on Parallel Computer. This memory system can migrate data between high speed memory as fast as cache memory and NUMA-type shared memory by the program for data migration. This memory system is composed by word-addressable high speed memory (Cache Level Memory) and hardware mechanism which executes instructions to migrate variable sized data In this paper, We evaluate performances between Our Proposed Memory System and Parallel Computer with Conventional Cache. We use Livermore loop benchmarks for these evaluation. As a result, it shows higher performance than conventional cache.

In the fetch instruction method, the branch is treated as the change of the destination address for instruction fetch. And fetch instructions instead of branch instructions are specified explicitly in a program code. Using a fetch instruction, the basic block to be fetched after the current block is specified. The processor pre-fetches the only necessary instructions as many as possible. This paper describes the basic of this method as well as the performance evaluation using trace examples.

We propose a new hierarchical memory system. In this memory system, two extra programs transfer the data among any hierarchical memories by one word. This System makes cache like memory utilization better than conventional cache memory systems, because the data which application programs just need are transfered to upper level memory. Simple bench-marks show that this system can execute the application programs 1.76 times faster than conventional cache memory systems.

In this paper, We propose Distributed Shared Memory based Multi-processor system which migrates data between high speed memory(cache like memory) and distributed shared memory by user program. Data Migration Unit is performed by user program and is able to migrate variable size of data. It makes two better characteristics than conventional cache memory; as follows. 1)Minimum and consistent data is always available in high speed memory (cache like memory). 2)Data Migration Unit can hide cache miss and cache coherent protocol overhead because DU and PU can perform simultaneously.

We have proposed a new hierarchical memory system, which consists of level memories. This system has two kinds of programs. One is target program which executes arithmetic and logical part. Another is data transfer programs which control data mapping and transfer between different levels of hierarchical memories by one word. Furthermore, data transfers are done in parallel with the target program. Therefore, it is possible for this system to prepare necessary data into upper level memory before the target program refers to them. In this paper, we propose optical programming strategies for this memory system and evaluate the programs which apply the strategies.

We propose a new branch method which is an approach to reduce the branch hazard in the pipelined processors. In this method, the processor can identify a branch instruction on fetch stage of pipeline and it begins to watch the determination of the branch condition. So it can begin to process the branch as soon as the branch condition is set. Because of this early branching method, the zero cycle branch may occur. This paper describes the instruction set architecture as well as the effect of this method with showing two sample programs.

The hypercube is a particularly versatile network topology for multicomputer sysytem. But the hypercube has a one drawback which is the number of nodes must be power of 2. In this paper, we present the extended hypercubes to lighten this limitation. While an r-dimensional hypercube can be constructed from two r-1-dimensional hypercubes, an extended hypercube can be constructed from an r-dimensional hypercube and an (r-1)-dimensional hypercube by connecting same as the hypercubes. The extended hypercube has a recursive structure like the hypercube. We also present embedding of rings, multidimensional arrays and complete binary trees in extended hypercubes.

A new hybrid processor based on VLIW and PN-superscalar is proposed. This processor fetches a program in the same way of VLIW processor, and it executes in the same way of PN superscalar processor. A program for this processor is similar to the ordinary VLIW program. But there is no execution barrier among the element instructions in a long word. The control dependency between any two instructions is written explicitly. So the execution order for all instructions is scheduled statically. And since the specification for this is not depended on the way of instruction fetch, the processor can run with the simultaneous execution of the element instructions which are fetched at the different cycle. This paper describes its processor architecture detail as well as the simulation result using software simulator.

We propose the method to make the parallel programs run efficiently in the Distributed Computing. When the parallel programs are executed on the distributed computer, this facility can enable the run-time system to utilize the characteristics of the parallel programs as well as the static and dynamic characteristics of the distributed system. For this purpose, our system has the mechanism that provides the static and dynamic information of the system where the program is running, then our system optimize the program performance by modification of the task allocation. Additionally the task characteristics, called Task Table, is defined by the programmer and can be utilized.

We introduce new concept HUMAN to the computer which conecting by the Internet, and making vartual society on the network. It is considered more easy to imitate the action of human by introducing shuch concept. We supporsed Service-man as a example of HUMAN living in vartual society. We considered how to realize Sa-ervice-man, what mechanism is requierd, and describe a protype of Service-man on a current compyuter and network system.

When we write a parallel program using a language with message passing facility and using the functional division scheme, processes of its program communicate the various amount of data with the various frequency. So, the run time allocation of the process to processor is important for this kind of programs. In this paper, we examine the run time system for parallel program in which the process migration is specified as well as its dynamic processor allocation scheme.

In general, a system is constructed as a collection of modules. If we can specify each module used in the system as a set of candidates, then whole system will get more flexibility. In this study, we discuss how we should represent the candidates, and propose a notation to specify the candidates through an expression consists of symbols for concept.

Distributed shared memory systems are remarkable, Because these Parallel systems accept exist programs with minimum modify. But Distributed shared memory systems have a disadvantage as data latency brought by both the size of these systems and the speed gap between memory and processor. To hide reference latency on a Distributed shared memory system, Software Prefetcing has been widely used. but this method requires overhead to issue prefetch instructions. We have already proposed a new Hardware unit based on data prefetching scheme for these systems. The basic idea is to place the Hardware unit which is able to execute load instructions before executed by processor. In this paper, We argue that how the unit executes prefetching when it meets conditioned Branch. because it's important to make full use of its ability. and We make a simulation of the Hardware unit on a CAD called PARTHENON.

Execution ability of processors has been getting higher and higher. As a result, it needs memories which is big size and can access within slight time. It is difficult to realize in its construction and its principle. So recently cache memory system is used. But, cache miss sometimes occurs in cache memory system. If cache miss occurs frecuently, it spoils the processor's abilty. One of the reasons why cache miss occurs frecuently is to replace the contains between cache memory and main memory by constant algorithm. Therefore the programmer who knows the data movement in the programs programs not only application program but also specified programs which replace the contains. That had better lead the slightest cache misses latency. In this paper, we propose the new memory system and argue the solution of the problem which the system have potentially. And then we show the simple performance review of this system. The result shows that this system can reduce the cache miss latency extremely.

In this paper, we describe a new programming language that was designed by introducing inheritance and rendezvous facilities into parallel processing language SPLAN. The goal of this language which treat autonomous objects as processes is to express the object-oriented model directly. This language adopt the extended rendezvous facility in which receiver is able to specify the communication partner.

SPLAN is a CSP and PASCAL based programming language for parallel computers. It is designed to be the concurrent programming language which is independent of the parallel architecture. Its program consists of concurrent processes. Each process is generated dynamically and can communicate another using channels which are allocated on generation time. This paper describes the language features as well as its implementation on a multiprocessor.