Motohiro Tomita, Shunsuke Oba, Yuya Himeda, Ryo Yamato, Keisuke Shima, Takehiro Kumada, Mao Xu, Hiroki Takezawa, Kohhei Mesaki, Kazuaki Tsuda, Shuichiro Hashimoto, Tianzhuo Zhan, Hui Zhang, Yoshinari Kamakura, Yuhhei Suzuki, Hiroshi Inokawa, Hiroya Ikeda, Takashi Matsukawa, Takeo Matsuki, Takanobu Watanabe
IEEE Transactions on Electron Devices, 65(11) 5180-5188, Nov, 2018 Peer-reviewedLead author
© 2018 IEEE. We propose a planar device architecture compatible with the CMOS process technology as the optimal current benchmark of a Si-nanowire (NW) thermoelectric (TE) power generator. The proposed device is driven by a temperature gradient that is formed in the proximity of a perpendicular heat flow to the substrate. Therefore, unlike the conventional TE generators, the planar short Si-NWs need not be suspended on a cavity structure. Under an externally applied temperature difference of 5 K, the recorded TE power density is observed to be 12 μW/cm2 by shortening the Si-NWs length and suppressing the parasitic thermal resistance of the Si substrate. The demonstration paves a pathway to develop cost-effective autonomous internet-of-things applications that utilize the environmental and body heats.