Naoto Matsuo

Low temperature (<= 400 degrees C) formation of orientation-controlled large (>= 10 gm) Ge-on-insulator (GOI) structures is desired to fabricate 3-dimensional large-scale integrated circuits (LSIs), where Ge-based functional devices are stacked on Si-LSIs. For this purpose, Si-seeded pulse-laser annealing (PLA) combined with low temperature substrate heating (<= 400 degrees C) has been developed. Here, a-Ge stripes on Si substrates partially covered with insulating films are subjected to PLA, where single edges of the a-Ge stripes directly contact Si seeding substrates through opening windows of insulating films. PLA at room temperature generates lateral growth of Ge layers from Si-seeding substrates. However, the growth length is short (similar to 1 pm), which is attributed to very short melting time. To increase the melting time, low-temperature (5400 C) substrate heating during PLA is examined. As a result, very large (similar to 20 gm) orientation-controlled GOI is obtained by combining substrate heating (400 C) with PLA. Detailed electron microscopy analysis reveals very high crystallinity of the grown layers. Consequently, high-quality rapid-melting growth of Ge becomes possible at a low processing temperature of similar to 400 C. This thermally-assisted (similar to 400 C) Si -seeded PLA will facilitate realization of 3 dimensional LSIs.