吉田 晴彦

The interface properties of strongly correlated electron system/band semiconductor junctions were investigated in the La_1−xSr_xVO₃/p-Si(100) structure. Spectroscopic observations show that the electronic structure of the interface is typical of insulator/semiconductor junctions for x ≤ 0.2 and Schottky junctions for x ≥ 0.25. For the forward current density–bias voltage (J–V) characteristics, energy barriers that were otherwise unexplainable by spectroscopy were estimated from the thermionic emission model fitting of the J–V characteristics, indicating that the injected carriers from Si to La_1−xSr_xVO₃ can also feel the correlation force of Coulomb repulsion at the interface.

Microscopic characterization of generation lifetimes in a SiO 2 /Si structure has been carried out using scanning capacitance microscopy (SCM). Generation lifetimes could be investigated by monitoring the capacitance transient due to inversion layer formation. The validity of local capacitance transient measurements by SCM was verified by comparing with the results of conventional capacitance transient measurements using a MOS capacitor. Furthermore, it was demonstrated that SCM can be used for imaging of the formation process of the inversion layer on a nanometer scale.

We studied the effective net charge density (Q(eff)) of strontium silicate (SrxSiOx+2, x = 1, 2, 3) films grown on silicon (Si) (100) substrates. The SrxSiOx+2 layers were deposited from a Sr2SiO4 polycrystalline target by pulsed laser deposition, and then annealed at 400-600 degrees C in an oxygen atmosphere with a tube furnace. The Qeff values of the SrxSiOx+2/Si (100) samples were obtained from the shift in the voltage of the flat band state in their capacitance-voltage curves. The SrxSiOx+2/Si (100) samples with a thickness of 15 nm annealed at 400 degrees C showed the maximum Q(eff)/q value of 1.03 X 10(13) cm(-2), where q is the elementary charge. With increasing annealing temperature, the SrxSiOx+2 layer penetrated into the Si (100) substrate. This penetration may degrade the interfacial properties and decrease the Qeff value of the layers. For all the samples, the charges concentrated near the SrxSiOx+2/Si (100) interface. Our results suggest that anion and cation migration plays an important role in charge generation at the SrxSiOx+2/Si (100) interface, consistent with the findings of a previously reported molecular dynamics calculation. Published by AIP Publishing.

The authors studied the correlation between the chemical bonding (CB) states and fixed charge (FC) states of Sr-silicate films grown on Si(100) substrates [Sr-silicate/Si(100)]. The Sr-silicate/Si(100) samples were synthesized by silicate reaction of SrO layers on the Si substrates through the diffusion of Si atoms from the substrates by thermal annealing in oxygen atmosphere. The CB states and the FC states of the Sr-silicate/Si(100) samples were obtained from their O 1s core-level x-ray photoemission spectra and the shift in voltage from the flat band state in their capacitance-voltage curves, respectively. Peak fittings of the O 1s core-level spectra for each sample were carried out with the three components of Si-O, Si-O-Sr, and Sr-O bonds to determine the CB state. The thin Sr-silicate layers were mainly constructed of the Si-O-Sr component. With increasing thickness, the amount of Si-O-Sr component decreased while that of Sr-O increased. The thickness dependency of the FC density showed a good agreement with that of the Si-O-Sr component, revealing a clear correlation between FC and Sr-O-Si bonding. Our results suggest that silicate bonding plays an important role in FC generation in Sr-silicate systems. (C) 2016 American Vacuum Society.

We investigated the room temperature growth of HfO2 layers on Si substrates by pulsed laser deposition under ultra-high vacuum conditions. The laser fluence (LF) during HfO2 layer growth was varied as a growth parameter in the experiments. X-ray photoemission spectroscopy (XPS) was used to observe the interface chemical states of the HfO2/Si samples produced by various LFs. The XPS results indicated that an interface Hf-silicate layer formed, even at room temperature, and that the thickness of this layer increased with increasing pulsed LF. Additionally, Hf-Si bonds were increasingly formed at the interface when the LF was more than 2 J/cm(2). This bond formation process was related to decomposition of HfO2 to its atomic states of Hf and O by multiphoton photochemical processes for bandgap excitation of the HfO2 polycrystalline target. However, the Hf-Si bond content of the interface Hf-silicate layer is controllable under high LF conditions. The results presented here represent a practical contribution to the development of room temperature processing of Hf-compound based devices. (C) 2016 Author(s). All article content, except where otherwise noted, is licensed under a Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

Contactless capacitance transient techniques have been applied to local mapping of interface traps of a semiconductor wafer. In contactless capacitance transient techniques, a Metal-Air gap-Oxide-Semiconductor (MAOS) structure is used instead of a conventional Metal-Oxide-Semiconductor (MOS) structure. The local mapping of interface traps was obtained by using a contactless Isothermal Capacitance Transient Spectroscopy (ICTS), which is one of the contactless capacitance transient techniques. The validity of the contactless ICTS was demonstrated by characterizing a partially Au-doped Si wafer. The results revealed that local mapping of interface traps using contactless capacitance transient techniques is effective in wafer inspection and is a promising technique for the development of MOS devices and solar cells with high reliability and high performance. (C) 2016 Author(s).

We fabricated a Y2O3-ZrO2 film (YZO) on Al2O3 to achieve the field effect passivation with high negative fixed charge densities on p-type Si. The surface recombination velocity was improved down to 30cm/s after annealing at 400 degrees C. This improvement can be attributed to the effective fixed charge enhancement while the interface state densities were kept almost constant. A high thermal tolerance of over 600 degrees C upon inserting a 2-nm-thick ZrO2 layer between the YZO and Al2O3 interface was confirmed. This result showed that the ZrO2 layer acts as a protective barrier to prevent Al and Y interdiffusions. Annealing at a higher temperature of 800 degrees C resulted in interface degradation and YZO crystallization, which led to the deterioration of the passivation properties. (C) 2016 The Japan Society of Applied Physics

Aluminum oxide (AlOx) films were deposited by mist chemical vapor deposition (MCVD) in air for p-type crystalline silicon, and the effects of the deposition temperature (T-dep) and AlOx film thickness on the maximum surface recombination velocities (S-max) were evaluated. It was found that S-max was improved with increasing T-dep. The AlOx film deposited at 400 degrees C exhibited the best S-max value of 2.8cm/s, and the passivation quality was comparable to that of AlOx deposited by other vacuum-based techniques. S-max was also improved with increasing film thickness. When the film thickness was above 10 nm, S-max was approximately 10 cm/s. From the Fourier transform infrared spectra, it was found that the AlOx films deposited by MCVD consisted of an AlOx layer and a Si-diffused AlOx layer. In addition, it is important for the layers to be thick enough to obtain high-quality passivation. (C) 2015 The Japan Society of Applied Physics

The passivation properties and band structures in aluminum oxide (AlOx) deposited by ozone-based atomic layer deposition (ALD) at room temperature on p-type crystalline silicon were investigated by X-ray photoelectron spectroscopy (XPS). The effective carrier lifetime depends on the thickness of AlOx films, since the field effects induced in the films by fixed charges depend on film thickness. The fixed charges are different by two orders of magnitude between films with thicknesses of 10 and 30 nm. At the 30-nm-thick AlOx/Si interface, the completely accumulated band bending of the Si surface was observed. On the other hand, a thin depletion layer was formed at the 10-nm-thick AlOx/Si interface. From the time-dependent XPS measurements, a hole trap was observed toward AlOx, in which trapping centers existed. (C) 2015 The Japan Society of Applied Physics

Recently, excellent surface passivation has been achieved for both p- and n-type silicon solar cells using AlOx/SiNx:H stacks deposited by atomic layer deposition and plasma-enhanced chemical vapor deposition. However, alternative materials and deposition methods could provide practical options for large-scale manufacturing of commercial solar cells. In this study we demonstrate that AlOx/AlNx stacks fabricated by reactive radio-frequency magnetron sputtering can provide fairly good surface passivation (S-max of similar to 30 cm/s) regardless of AlOx thickness, which is found to be due to the high negative fixed charge density (Q(eff) of -2.8 x 10(12) cm(-2)) and moderately low interface trap density (D-it of 2.0 x 10(11) eV(-1).cm(-2)). The stacks also show fairly good antireflection performance in the visible and near-infrared spectral region. The demonstrated surface passivation and antireflection performance of in situ reactively sputtered AlOx/AlNx stacks make them a promising candidate for a surface-passivating antireflection coating on silicon solar cells. (C) 2015 The Japan Society of Applied Physics

We fabricated Y2O3-ZrO2 composition film (YZO) on Al2O3 for the field effect passivation with high negative fixed charge densities on p-type Si. The surface recombination velocity was improved down to 30 cm/s after annealing at 400 degrees C. High thermal tolerance was confirmed over 600 degrees C by inserting 2-nm-thick ZrO2 layer between YZO and Al2O3 interface. This result showed ZrO2 layer work as protecting barrier of Al and Y interdiffusions.

We investigated stacking double layer structure, the Y2O3-ZrO2 composite film (YZO) on AlOx, for the field effect passivation with high negative fixed charge densities on p-type Si. The composition spread YZO films were deposited at room temperature by using combinatorial sputtering technique. The fixed charge densities were extracted from the flat band voltage shift in the capacitance-voltage characteristics. The as-deposited ZrO2 film incorporated with 15% Y2O3 stacking on the ALD AlOx structure showed the highest negative fixed charge of -1.9 × 1012 cm-2. The field effect passivation can be controlled by the negative fixed charges in the YZO film depending on the composition and dipole uniformly formed at AlOx/Si interface. After annealing in the oxygen atmosphere, passivation properties deteriorated caused by the Al diffusion at the YZO/AlOx interface.

The effects of interface properties such as a negative fixed charge density and an interface trap density on the surface passivation of crystalline Si by O-3-based batch ALD AlOx were studied. High-quality surface passivation with S-max of similar to 10cm/s was obtained from the AlOx samples deposited at 200 degrees C after annealing. This feature is attributed to the excellent field effect passivation by the high negative fixed charge density of similar to-5 x 10(12)cm(-2) and chemical passivation, which reduces the interface trap density to similar to 1 x 10(11)eV(-1)cm(-2). The annealed AlOx samples deposited at 200 degrees C also show high thermal stability during firing at 850 degrees C. Additionally, we found that the formation of a thin SiOx interlayer is essential for the formation of a high negative fixed charge density that induces strong field effect passivation, and that defect passivation at the Si/SiOx interface by diffused hydrogen from AlOx layers is the origin of chemical passivation. (C) 2014 The Japan Society of Applied Physics

We studied the structure of ozone-based atomic layer deposited aluminium oxide (AIO(x)) films as a passivation layer for p-type crystalline silicon (c-Si) solar cells and focused on the differences in the structure by the production conditions of AIO(x) films. Carbon (C)-related groups such as methyl, hydroxyl, and carboxyl groups which originate from the aluminium source, trimethylaluminium, were only found in the AIO(x) film deposited at room temperature (AT-sample). By post-deposition thermal annealing (PDA), the C-related groups were desorbed from the film and a part of their space remained as voids. The C-related groups were not found in the films deposited at 200 or 300 degrees C (heated-samples) since they were desorbed during the deposition. Even though C-related groups did not exist in the both RT- and heated-samples after PDA, the structure of the AIO(x) film of the RT-sample was different from that of the heated-sample. (C) 2013 The Japan Society of Applied Physics

To investigate the effect of initial oxidized layer condition on passivation quality of AlOx films deposited at room temperature by means of ozone-based atomic layer deposition technique, crystalline silicon substrates were exposed to ozone before deposition. This ozone exposure pre-treatment increased the thickness of over-layer as compared with standard samples, and deteriorate interface quality of as-deposited samples. For 10nm-thick samples, the ozone exposure pre-treatment is effective for generation of negative fixed charges. The effective lifetime of the sample with ozone exposure and post-deposition annealing is 1.8 msec at the injection level of 1015 cm-3. For 30nm-thick samples, ozone exposure pre-treatment improves the effective lifetime. © 2013 IEEE.

Although crystalline silicon is widely used as substrate material for solar cell, many defects occur during crystal growth. In this study, the generation of crystalline defects in silicon substrates was evaluated. The distributions of small-angle grain boundaries were observed in substrates sliced parallel to the growth direction. Many precipitates consisting of light elemental impurities and small-angle grain boundaries were confirmed to propagate. The precipitates mainly consisted of Si, C, and N atoms. The small-angle grain boundaries were distributed after the precipitation density increased. Then, precipitates appeared at the small-angle grain boundaries. We consider that the origin of the small-angle grain boundaries was lattice mismatch and/or strain caused by the high-density precipitation. © 2012 American Institute of Physics.

We have investigated the effects of deposition temperature and post-annealing on the passivation performance of AlOx films deposited by O-3-based atomic layer deposition for crystalline Si. We found that the dramatic enhancement in the passivation performance of room-temperature deposited AlOx films by post-annealing is due to the phase transformation of aluminum silicate to mullite in an AlOx interlayer and the resulting self-aligned AlOx/SiOx interface. This result is interesting for the fabrication of high-performance silicon solar cells with AlOx passivation layers. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.3701280]

AlOx films as passivation layers for p-type crystalline silicon were prepared by atomic layer deposition with ozone as an oxidant, and the effects of the AlOx film thickness and deposition temperature on the maximum recombination velocity (S-max) were evaluated. S-max is improved by increasing the layer thickness but saturates at a layer thickness of about 30 nm. In the case of samples deposited at room temperature, S-max is improved fivefold when the thickness is increased from 20 to 33 nm. S-max also improved as the deposition temperature was increased to 300 degrees C then deteriorated when it was further increased to 350 degrees C. After postdeposition annealing, we obtained an Smax of 8.5 cm/s. (C) 2012 The Japan Society of Applied Physics

We investigated the new materials applicable for the field effect passivation layer in crystalline Si solar cells, ZrO2-Al2O3 and ZrO2-Y2O3 binary systems, by using combinatorial synthesis method. As-deposited samples indicated hysteresis curves and flat band-voltage (V-FB) shifts at capacitance-voltage (C-V) measurements. After oxygen gas annealing (OGA) at 700 degrees C for 5min, an improvement of the hysteresis and a positive shift of V-FB were observed. OGA process influenced defects density related to decreasing oxygen vacancy. OGA processed ZrO2 incorporated with 20% Al2O3 and 15% Y2O3 structures showed the maximized negative fixed charge of-5.8 X 10(12) cm(-2) and -7.8 X 10(12) cm(-2) in each system, respectively, suggesting that the ZrO2 based alloy systems were revealed to be the promising material for the passivation in the solar cell application.

We evaluated the three types of composition spread passivation layer, i.e., Al2O3-HfO2, HfO2-Y2O3, and Al2O3-Y2O3 systems, by combinatorial pulsed laser deposition to evaluate and control the fixed charge, while interface states were kept constant with a SiO2 interlayer. The flat-band voltage of the capacitance-voltage (C-V) curves was shifted widely from positive to negative by changing the composition. The calculated fixed charge in the Y2O3 was positive while those in the HfO2 and Al2O3 were negative. In the Al2O3-Y2O3 system, the fixed charge was significantly varied between -2.7 and 1.3 x 10(12) cm(-2) with composition spread. The maximum negative charge was found in the Al2O3 layer with a slight amount of Y2O3, while the maximum positive charge was realized with almost pure Y2O3. The fixed charge modifications were also found in the Al2O3-HfO2 and HfO2-Y2O3 systems. Additional oxidation after layer deposition also modified the fixed charge properties. The largest negative fixed charge of -3.1 x 10(12) cm(-2) was found in approximately HfO2 : Y2O3 = 1 : 1 after the annealing process, while the largest positive charge of 1.3 x 10(12) cm(-2) was found for Y2O3 with Al2O3 incorporation. The passivation layers with controlled fixed charge can be promising materials for the high-quality passivation layer in crystalline silicon solar cells. (C) 2011 The Japan Society of Applied Physics

A scanning capacitance microscopy (SCM) has been applied to the electrical characterization of passivation films for crystalline Si solar cells. An Y 2O3-Al2O3 system, which is a binary composition spread oxide film, was used as a fixed-charge-controlled passivation film. The flat-band voltages of the Y2O3-Al 2O3 system were determined from microscopic C-V curves measured by the SCM. The result was in agreement with that of a conventional C-V method. Additionally, the dV/dC images measured by the SCM were investigated for visualizing the spatial distribution of interface trap density. © 2011 IEEE.

A contactless Zerbst method has been developed to characterize the generation lifetime and the surface generation velocity of a semiconductor wafer. This characterization is unaffected by the gate leakage current or the device fabrication process. In this study, this contactless Zerbst method was used to characterize the generation lifetime and the surface generation velocity of a partially Au-doped Si wafer. The results demonstrate that the contactless Zerbst method is a powerful technique for characterizing the generation lifetimes and the surface recombination velocities of semiconductor wafers.

Scanning capacitance microscopy (SCM) using a dV/dC signal has been proposed for local mapping of interface traps in an insulator/semiconductor structure. In conventional SCM measurements using a dC/dV signal, it is difficult to accurately analyze the spatial distribution of interface traps from the obtained SCM images because the dC/dV signal is inversely proportional to the interface trap density. In the proposed technique, however, the spatial distribution of the interface traps can be characterized using the dV/dC signal, which is directly proportional to the interface trap density. The effectiveness of the proposed technique has been demonstrated by characterizing the spatial distributions of the interface traps in HfSiO/Si structures before and after H(2) annealing. The dV/dC images obtained reveal that the spatial variation in the interface trap density is reduced by H2 annealing. Consequently, SCM measurements using a dV/dC signal have been verified to effectively characterize the spatial distribution of interface traps. c 2009 American Institute of Physics. [DOI: 10.1063/1.3122597]

Energy band structure of gallium arsenide crystals is calculated by the discrete variational (DV)-X alpha molecular orbital method using a Madelung potential. By the use of the Madelung potential technique we found a possibility to be able to obtain energy band gaps close to the intrinsic values in the case of GaAs crystal. We then applied the technique to Zn-doped GaAs crystal with external strain and investigated an acceptor level as a function of the magnitude of external strain induced. By this investigation, we found a possibility that the acceptor level becomes shallower by the introduction of the external strains.. The application of the Madelung potential to the semiconductor crystals is the first trial and the related technical procedures have not yet been established. Therefore, further investigations on this technique are to be continued.

High-resolution photoluminescence (PL) mapping measurement was performed to study the gettering effect of polycrystalline Si on ultrathin silicon-on-insulator (SOI) wafers. A 150-mm-diam Unibond SOI wafer was patterned and partially gettered by polycrystalline Si process at 600 degreesC for 1 h. Then the wafer was annealed in H-2 atmosphere at 400 degreesC for 1 h. PL mapping clearly demonstrated the difference between the gettered and ungettered parts, before and after H-2 annealing. Before H-2 annealing, almost no variation was obvious between the gettered and ungettered parts. After H-2 annealing, however, we found the PL intensity was substantially increased, and the gettered area gave 24.7% higher PL intensity than the ungettered part. This coincided with the results of charge pumping measurements, which indicated a negligible difference of the interface trap density for the two areas before H-2 annealing, while remarkable decrease of this density for the gettered region after H-2 annealing. H-2 annealing thus decreased the interface trap density, and made the gettering effect more obvious. This result indicated that PL mapping is effective and sensitive in characterizing the gettering effect of ultrathin SOI structures. (C) 2004 American Institute of Physics.

Scanning capacitance microscopy (SCM) has been applied to microscopic characterization of electrical properties of silicon-on-insulator (SOI) wafers. Two kinds of capacitance-voltage (C-V) methods have been proposed for separately characterizing the electrical properties of a gate oxide, an SOI layer, a buried oxide (BOX) layer, a Si substrate, and their interfaces: (i) a front-gate C-V method whereby the electrical properties of the gate oxide and front SOI (the gate oxide/SOI) interface can be characterized., and (ii) a back-gate C-V method for the characterization of the electrical properties of the BOX layer, back SOI (the BOX/SOI) interface, and the BOX/Si substrate interface. Furthermore, SCM images of the sampled SOI wafer have been obtained for visualizing the microscopic spatial distribution of electrical properties of SOI wafers by using the proposed C-V methods. These SCM images revealed the fluctuation in the oxide charges and interface traps. SCM has been demonstrated to be an effective tool for microscopic electrical characterization of SOI wafers.

A novel gettering technique for a thin silcon-on-insulator (SOI) wafer is proposed. The gettering procedure for 1 h at 600degreesC using polycrystalline silicon film is followed by protection of the device region where the film is immediately removed after the procedure from the SOI wafer. Gettering was evaluated by comparing electrical properties of devices in gettered and ungettered parts of the wafer where half of the wafer was gettered. A detectable reduction of an off-current was observed in the gettered parts. The gettering effect was supported by the reduction of the localized state density measured by the charge pumping method. (C) 2004 The Electrochemical Society.

We investigated the correlation between optical lifetime and interface trap density in silicon-on-insulator (SOI) wafers. The temporal decay of electron-hole droplet (EHD) luminescence exclusively from the ultrathin superficial Si layer was measured under pulsed ultraviolet laser excitation. The interface trap density of the SOI wafers in the area adjacent to the luminescence measurement region was determined by the charge-pumping method. For such wafers, the lifetime increases as the trap density decreases. The correlation between the two values is discussed on the basis of the recombination process for EHD in the SOI structure.

A capacitance-frequency (C-f) method is applied to characterize heavy metal contamination. As is well known, the so-called low-frequency C-V characteristics is occurred when the generation of the minority carriers is able to keep up with the measuring frequency under the inversion condition. Namely, the shorter the generation lifetime is, the higher the frequency at which the low-frequency C-V characteristics occur is. In this study, the characterization of generation lifetime, interface traps, and bulk traps based on the C-f measurement is carried out. When the carrier generation from the interface traps and bulk traps are able to keep up with the measuring frequency, the influence of the interface traps and bulk traps also appears in the C-V characteristics. The validity of this method is assured with the use of Cu-doped and Au-doped samples.

A novel scanning charge-pumping method using one or more extra contactless gates is proposed for silicon-on-insulator (SOI) wafer inspection. In the proposed method, a contactless gate electrode is used as a measuring gate instead of the permanent gate electrode of normal metal-oxide-semiconductor transistors, allowing a wafer map of interface trap density to be obtained. A preliminary study is carried out using a sample device having two extra-gate electrodes in the close vicinity of a measuring gate electrode, which are contacted on an oxidized SOI wafer. The results demonstrate that the proposed method is a promising technique for the characterization of interface trap density in SOI wafers.

Cross-sectioned silicon-on-insulator (Sol) wafers were examined by a combination of scanning probe techniques, namely scanning capacitance microscopy (SCM), scanning resistance microscopy (SRM) and Kelvin probe force microscopy (KFM). Tests were conducted using bonded Sol and separation by implanted oxygen (SIMOX) wafers. SCM images identified the depletion layer at the SOI-buried-oxide (BOX) interface, and the thickness of the depletion layer was found to vary according to the bias voltage applied to the Si substrate. SRM images identified the high-resistance region in the Sol wafers, and KFM resolved the charge distribution, revealing that Sol wafers hold inherent positive charge. The locations of positive charge accumulation were found to differ between the two types of Sol wafers. Based on the results of this study, the use of multiple scanning probe techniques represents a promising tool for sub-micron-scale electrical characterization of Sol wafers. (C) 2002 Published by Elsevier Science B.V.

Local electrical characterization of silicon-on-insulator (SOI) was implemented using scanning probe techniques. We used combinations of scanning probe microscopy, which are scanning capacitance microscopy (SCM), scanning resistance microscopy (SRM) and Kelvin force microscopy (KFM). Two kinds of SOI wafers were sampled. They are bonded SOI and separation by implanted oxygen (SIMOX) wafers. The SCM image showed contrast variation at the SOI/buried oxide (BOX) interface. Detailed analysis of the contrast variation as a function of the bias voltage applied to the Si substrate indicated that a depletion layer is formed in the SOI region in as-fabricated state. We also ascertained the high-resistance region in the SOI wafers using the SRM. Profiles of the SRM images showed that spread of the high resistive region depends on the bias voltage. These results. suggest that the BOX layer inherently holds positive charges. The surface potential distribution observed by KFM identified that the locations of positive charge accumulation were different between the two types of SOI wafers. This difference in the location of the positive charges might be caused by the difference in the fabrication process of SOI wafers.

A novel charge pumping method without using MOS transistors is proposed for obtaining a spatial distribution of interface traps in an SOI wafer. The proposed method can be performed without fabrication processes for the source/drain of MOS transistors that are essential for conventional charge pumping methods. In this method, Schottky contacts are used instead of the normal source/drain diffused layer. The results demonstrate that the proposed method is effective in applying to SOI wafer inspection.

A scanning charge pumping method using a back channel is proposed for the characterization of interface traps in a silicon-on-insulator (SOI) wafer. In this method, a contactless gate electrode is used instead of the permanent gate electrode of normal metal-oxide-semiconductor transistors, allowing the interface trap density of SOI wafers to be mapped. A preliminary study is performed using a sample device with many permanent gate electrodes fabricated on an oxidized SOI wafer. The results demonstrate that the back-channel-type scanning charge pumping method is effective in characterizing interface trap density and is potentially applicable to SOI wafer inspection. (C) 2001 American Institute of Physics.

We have developed two new electrical characterization methods for thin SOI wafers. They are the scanning charge pumping (SCP) method and revised scanning capacitance microscopy (SCM). With the use of SCP, we could perform SOI wafer inspection using a movable gate electrode, in contrast to the conventional charge pumping method. Our feasibility studies of SCP have been successful. Difficulties regarding minority carrier injection due to the use of the movable gate electrode were conquered by the use of an inversion layer (channel) controlled by the extra gate instead of the source/drain of an MOS transistor. Using the revised SCM, we were able to find a new capacitance versus voltage (C-V) curve of an SOI wafer, from which we could obtain submicron-scale information on the electrical properties of the wafer.

Time-based measurements are commonly used for lifetime characterization of semiconductors. We have developed the theory; verified by experiment, of frequency-based lifetime characterization as an alternative to time-based measurements for MOS devices biased in inversion, One consideration during lifetime/diffusion length measurements, is whether the near-surface space-charge region or the bulk or quasineutral region is characterized. To characterize the near-surface space-charge region of the three, one usually makes room temperature pulsed MOS capacitor or diode leakage current measurements, We show that room-temperature, frequency-domain capacitance, conductance, or resistance measurements characterize the quasineutral bulk, not the space-charge region, in contrast to room-temperature pulsed MOS-C or diode leakage curl ent measurements which characterize the space charge region.

Interface traps and built: traps induced by heavy metal impurities in SI-MOS structure were characterized by isothermal capacitance transient spectroscopy (ICTS). In addition, the use of an MOS inversion time is proposed for the detection of a very low density of heavy metal impurities in the ICTS measurements. It is shown that heavy metal impurities enhanced interface trap densities as well as induced bulk traps. The degree of the enhancement varies with the species of heavy metal impurities. Interface traps may be enhanced by the substitutional heavy metal impurities. Moreover, it has been ascertained that a very low level of contamination by heavy metals can be detected by using the MOS inversion time. This has been experimentally shown by the use of a copper impurity. Furthermore, it has been clarified from the change of MOS inversion time that interface traps are also detrimental to the carrier generation lifetime. (C) 2000 Scripta Technica.

The detection sensitivity of contactless transient spectroscopy (COLTS) to localized states was investigated in detail. We first point out that the detection sensitivity of conventional capacitance transient spectroscopy to interface traps is greatly degraded as oxide thickness is very thin. This is a serious problem for the electrical characterization of recent MOS devices with an ultra-thin gate oxide. In this study, we found that COLTS measurements could overcome this problem: we determined that high detection sensitivity to the interface traps could be maintained using an optimal air gap in the COLTS measurements even when the oxide film is very thin. This is because maximal sensitivity is obtained at the optimal oxide thickness of around 300 nm in conventional capacitance transient spectroscopy. This shows that COLTS can become a highly sensitive tool for interface traps in advanced MOS devices with an ultra-thin gate oxide. In addition, actual COLTS measurements were performed using an oxidized n-type Si wafer doped with gold impurity. Experimental results support the dependence of the detection sensitivity on an air gap which is predicted by theoretical calculation. (C) 2000 Elsevier Science B.V. All rights reserved.

We have succeeded in obtaining first-ever signals of COntactLess Transient Spectroscopy (COLTS) using an MIOS structure which is composed of metal, insulating helium gas, oxide, and silicon wafer. Feasibility test was carried out using a gold-doped CZ silicon wafer. The insulating air (helium gas) gap was controlled to be less than one micrometer using piezo-electric actuators with the help of a capacitance measurement in which three parallelism electrodes were prepared besides a reference electrode far COLTS measurements. It is plausible that COLTS measurements are indispensable for the wafer characterization and in-line monitoring of electrically active impurities in the advanced ULSI age. This is because electrodes might degrade surface properties, the oxide film, and interface properties during the fabrication and the characterization of the device.